Conventionally, in a semiconductor integrated circuit, high performance and a small chip area are realized by designing a dedicated LSI, and a low manufacturing cost is realized by mass production. However, it is necessary to develop the integrated circuit individually according to each application. The cost for development is increasing. Further, it is not easy to change the function in the dedicated LSI. In general, when it is required for the LSI to change the function, a part of or a whole of the design and the manufacturing process have to be reconstructed.
When the function in a FPGA (field programmable gate array) is changed, it is not necessary to re-execute the manufacturing process, but it is necessary to re-execute the designing process after the RTL design. Specifically, in the timing design, the length of an wiring channel for connecting between logic elements is not clear until the logic elements are laid out. In general, since a roundabout amount of the wiring channel path is large, an operating frequency of the FPGA is low, compared with the dedicated LSI and ASIC. Thus, a difficulty arises such that the maximum operating frequency of the FPGA may be varied at every time when the FPGA is re-designed. Further, since a large channel region is necessary to couple between logic elements, a chip area of the FPGA is a few times or ten times larger than the dedicated LSI, and therefore, it is difficult to reduce a cost of the FPGA.
The function change in the processor or a DSP is flexibly possible in a process executed by a soft ware, and general versatility is high, so that mass production is possible, and a cost is low in general. However, the processor and the DSP have poor performance for executing a calculation per one bit unit, compared with logical operation per one register unit and product-sum operation. Further, it is difficult to obtain sufficient performance for executing a complicated communication processing and an advanced image processing, compared with the dedicated LSI. In order to increase the performance, an approach to increase an operating frequency is generally used. However, a difficulty arises such that this approach provides to increase electric power consumption.
It is possible for a DRP (dynamic reconfigurable processor) to manage a function change, so that the DRP is favorable to execute high speed processing, compared with a soft ware processing with using a conventional processor. However, the number of elements for providing a logical reconfiguration unit in pervious products of the DRP is 16 to 1024, and therefore, the number of elements is smaller than the FPGA. Thus, the DRP has a difficulty with flexibility. Further, a comparatively large wiring channel region for coupling between logical reconfiguration elements is necessary. In some cases, a roundabout amount of the wiring for coupling via the wiring channel may be large. Thus, a transmission delay of a signal as a critical path is large, so that a difficulty arises such that it is difficulty to increase the operating frequency, compared with the dedicated LSI. Further, a wiring channel region for coupling between a configuration memory for the logical reconfiguration element and the logical reconfiguration element is necessary. Thus, in general, the area is larger than the dedicated LSI and the ASIC. Thus, a difficulty arises such that it is difficult to reduce the cost.